The present invention relates to a display device using thin film transistors. Among display devices having pixels provided with a thin film transistor and arranged in a matrix configuration, there are liquid crystal display devices using liquid crystal, and display devices of the EL type using electroluminescence.
FIG. 16 shows a first conventional liquid crystal display device using thin film transistors. In this liquid crystal display device, thin film transistors are arranged in an array on one of two opposing transparent glass substrates (not shown), and a transparent counter electrode is disposed on the other of the two opposing transparent glass substrate. The liquid crystal display device needs polarizers and a backlight as its constituent parts in addition to a display panel formed of the two opposing transparent substrates, but those constituent parts are not directly related to the present invention, and therefore in the subsequent explanation, the one of the two substrates formed with the thin film transistors is referred to as the display panel.
In FIG. 16, fabricated on the display panel LCP are a plurality of scanning lines GL extending horizontally and a plurality of drain lines DL extending vertically. Thin film transistors TFT are fabricated in the vicinities of intersections of the scanning lines GL and the drain lines DL. A gate of each of the thin film transistors is connected to a corresponding one of the scanning lines GL, and one of a drain and a source of each of the thin film transistors is connected to a corresponding one of the drain lines DL, and the other of the drain and the source is connected to a pixel electrode. A plurality of pixels each having the thin film transistor TFT and the pixel electrode are arranged in a matrix configuration on the crystal display panel LCP. Shown in FIG. 16 are pixels PXR for displaying red images, pixels PXG for displaying green images, and pixels PXB for displaying blue images coupled to respective scanning lines GL, among the pixels arranged in the matrix configuration. A trio of the pixel PXR, the pixel PXG and the pixel PXB forms a picture dot. In an actual display area DPA, the trios are formed in a repeating configuration.
In operation of displaying, video signals supplied to the drain lines DL are applied to the pixel electrodes by selecting one of the scanning lines GL, and thereby turning on the thin film transistors TFT connected to the selected scanning line GL. As a result, a liquid crystal composition sandwiched between the pixel electrodes and the counter electrode is driven, and thereby light transmission between the pixel electrodes and the counter electrode is controlled, and consequently, a display is produced.
The scanning lines GL extends outside of the display area DPA formed with the pixels arranged in a matrix configuration, and are coupled to gate drivers VSR outside of the left and right sides of the display area DPA. The drain lines DL also extend outside of the display area DPA. In this liquid crystal display device, the drain lines DL coupled to pixels for displaying red, green, and blue images are connected to one terminal of switches SWR, SWG, and SWB, respectively. The other terminals of the three switches SWR, SWG, and SWB connected to the drain lines DL for a red (R) signal, a green (G) signal and a blue (B) signal, respectively, are connected together and connected to one of video signal input terminals VIDEOIN formed on the display panel LCP.
The switches SWR associated with the pixels PXR for displaying red images are controlled by a signal Φ1, the switches SWG associated with the pixels PXG for displaying green images are controlled by a signal Φ2, and the switches SWB associated with the pixels PXB for displaying blue images are controlled by a signal Φ3. All the drain lines DL coupled to the pixels PXR for displaying red in the display area DPA are coupled to corresponding ones of the video signal input terminals VIDEOIN via the respective switches SWR controlled by the signal Φ1, all the drain lines DL coupled to the pixels PXG for displaying green in the display area DPA are coupled to corresponding ones of the video signal input terminals VIDEOIN via the respective switches SWG controlled by the signal Φ2, and all the drain lines DL coupled to the pixels PXB for displaying blue in the display area DPA are coupled to corresponding ones of the video signal input terminals VIDEOIN via the respective switches SWB controlled by the signal Φ3. In other words, each of the video signal input terminals VIDEOIN is coupled to the three drain lines DL coupled to the three pixels for displaying red (R) signals, green (G) signals and blue (B) signals via the three switches SWR, SWG, SWB controlled by the three signals Φ1, Φ2 and Φ3, respectively.
The video signal input terminals VIDEOIN formed on the display panel LCP are connected to terminals of tape carrier packages TCP1, TCP2 and TCP3, and are connected to drain drivers DRV1, DRV2 and DRV3 (numerical suffixes 1, 2, 3, . . . will be sometimes hereinafter dropped where confusion can hardly arise) mounted on the tape carrier packages TCP1, TCP2 and TCP3 via wiring thereon. In FIG. 16, the video signal input terminals VIDEOIN and the terminals of the terminals of the tape carrier packages TCP1, TCP2 and TCP3 are separated from each other, but in practice they are connected to each other as by anisotropic conductive sheets. The three signals Φ1, Φ2 and Φ3 for controlling the switches SWR, SWG and SWB formed on the display panel LCP are supplied from an external control circuit TCON external to the display panel LCP.
FIG. 15 shows an internal structure of the drain driver DRV. The drain driver includes an input latch I-LTC for holding video data in digital form supplied from an external circuit, an output latch P-LTC for receiving the video data from the input latch I-LTC, and digital-to analog converters DAC for converting the video data held in the output latch P-LTC into analog signals for the purpose of supplying video signals to the video signal input terminals VIDEOIN of the display panel LCP.
In this display device explained above, during a period when a given one of the scanning lines GL is selected, first a first kind of video signals supplied from the drain drivers DRV1, DRV2, DRV3 are written into the red-displaying pixels PXR via the switches SWR by turning the signal Φ1 into an ON state, then during the same period when the given one of the scanning lines GL is selected, a second kind of video signals supplied from the drain drivers DRV1, DRV2, DRV3 are written into the green-displaying pixels PXG via the switches SWG by turning the signal Φ2 into an ON state, and then during the same period when the given one of the scanning lines GL is selected, a third kind of video signals supplied from the drain drivers DRV1, DRV2, DRV3 are written into the blue-displaying pixels PXB via the switches SWB by turning the signal Φ3 into an ON state. In other words, during a period when a given one of the scanning lines GL is selected, the drain drivers DRV output video signals for the red-displaying pixels PXR, video signals for the green-displaying pixels PXG, and video signals for the blue-displaying pixels PXB sequentially, in a time-division-multiplexed fashion. This configuration makes it possible to reduce the number of the drain drivers DRV to one third of the number of drain drivers required in a conventional display device.
FIG. 13 shows a second conventional liquid crystal display device. This liquid crystal display device also includes a plurality of scanning lines GL, a plurality of drain lines DL, and a plurality of pixels each provided with a thin film transistor and a pixel electrode, and the scanning lines GL are connected to two gate drivers VSR. This second conventional liquid crystal display device differs from the above-explained first conventional liquid crystal display device in that the display area LCP of the second conventional liquid crystal display device is divided into a plurality of display blocks.
In the second conventional liquid crystal display device, each of the display blocks has a plurality of drain lines DL, each of which is connected to one terminal of a corresponding one of a plurality of switches outside of the display area DPA. The other terminal of each of the switches is connected to a corresponding one of a plurality of drain bus conductors. The switches connected to the drain lines DL in the same display block are controlled by a common signal.
In the second conventional liquid crystal display device, the display area DPA is divided into three display blocks BK1, BK2 and BK3, in each of which n picture dots are coupled to each of the scanning lines GL.
In a first display block BK1 shown in FIG. 13, there are red-displaying pixels PR1, PR2, . . . , PRn, green-displaying pixels PG1, PG2, . . . , PGn, and blue-displaying pixels PB1, PB2, . . . , PBn, all of which are coupled to the same one of the scanning lines GL. The drain lines DL coupled to the red-displaying pixels, the green-displaying pixels, and the blue-displaying pixels are coupled to bus conductors BR1, BR2, . . . , BRn, bus conductors BG1, BG2, . . . , BGn, and bus conductors BB1, BB2, . . . , BBn, of a drain bus, via switching elements SR1, SR2, . . . , SRn, switching elements SG1, SG2, . . . , SGn, and switching elements SB1, SB2, . . . , SBn, respectively, outside of the display area DPA.
In a second display block BK2 shown in FIG. 13, there are red-displaying pixels PRn+1, PRn+2, . . . , PR2n, green-displaying pixels PGn+1, PGn+2, . . . , PG2n, and blue-displaying pixels PBn+1, PBn+2, . . . , PB2n, all of which are coupled to the same one of the scanning lines GL as in the first display block BK1. The drain lines DL coupled to the red-displaying pixels, the green-displaying pixels, and the blue-displaying pixels are coupled to the bus conductors BR1, BR2, . . . , BRn, the bus conductors BG1, BG2, . . . , BGn, and the bus conductors BB1, BB2, . . . , BBn, of the drain bus, via switching elements SRn+1, SRn+2, . . . , SR2n, switching elements SGn+1, SGn+2, . . . , SG2n, and switching elements SBn+1, SBn+2, . . . , SB2n, respectively, outside of the display area DPA.
In a third display block BK3 shown in FIG. 13, there are red-displaying pixels PR2n+1, PR2n+2, . . . , PR3n, green-displaying pixels PG2n+1, PG2n+2, . . . , PG3n, and blue-displaying pixels PB2n+1, PB2n+2, . . . , PB3n, all of which are coupled to the same one of the scanning lines GL as in the first display block BK1. The drain lines DL coupled to the red-displaying pixels, the green-displaying pixels, and the blue-displaying pixels are coupled to the bus conductors BR1, BR2, . . . , BRn, the bus conductors BG1, BG2, . . . , BGn, and the bus conductors BB1, BB2, . . . , BBn, of the drain bus, via switching elements SR2n+1, SR2n+2, . . . , SR3n, switching elements SG2n+1, SG2n+2, . . . , SG3n, and switching elements SB2n+1, SB2n+2, SB3n, respectively, outside of the display area DPA.
As explained above, since there are n bus conductors for red signals, n bus conductors for green signals, and n bus conductors for blue signals, a total of 3n bus conductors are formed outside of the display area DPA. The respective bus conductors of the drain bus are connected to corresponding ones of output terminals of the drain drivers.
On-or-off control of the plural switches SR1, SG1, SB1, SR2, SG2, SB2, . . . , SRn, SGn, SBn coupled between the drain lines in the first display block BK1 and the drain bus is performed by a signal Φ1, on-or-off control of the plural switches SRn+1, SGn+1, SBn+1, SRn+2, SGn+2, SBn+2, . . . , SR2n, SG2n, SB2n coupled between the drain lines in the second display block BK2 and the drain bus is performed by a signal Φ2, and on-or-off control of the plural switches SR2n+1, SG2n+1, SB2n+1, SR2n+2, SG2n+2, SB2n+2, . . . , SR3n, SG3n, SB3n coupled between the drain lines in the third display block BK3 and the drain bus is performed by a signal Φ3. The signals Φ1, Φ2 and Φ3 are supplied by an external control circuit TCON. The drain lines DL in each of the display blocks, the switches coupled between the drain lines DL and the drain bus, the drain bus conductors, and the output terminals of the drain drivers DRV are equal in number. The display blocks BK1, BK2, . . . and the control signals Φ1, Φ2, . . . are equal in number.
In this liquid crystal display device explained above, during a period when a given one of the scanning lines GL is selected, initially a first group of video signals supplied from the drain driver DRV to the drain bus are written into pixels of the first display block BK1 via the switches SR1, SG1, SB1, SR2, SG2, SB2, . . . , SRn, SGn, SBn coupled to the drain lines DL in the first display block BK1 by turning the signal Φ1 into an ON state, then, during the period when the given one of the scanning lines GL is selected, a second group of video signals supplied from the drain driver DRV to the drain bus are written into pixels of the second display block BK2 via the switches SRn+1, SGn+1, SBn+1, SRn+2, SGn+2, SBn+2, . . . , SR2n, SG2n, SB2n coupled to the drain lines DL in the second display block BK2 by turning the signal Φ2 into an ON state, and then, during the period when the given one of the scanning lines GL is selected, a third group of video signals supplied from the drain driver DRV to the drain bus are written into pixels of the third display block BK3 via the switches SR2n+1, SG2n+1, SB2n+1, SR2n+2, SG2n+2, SB2n+2, . . . , SR3n, SG3n, SB3n coupled to the drain lines DL in the third display block BK3 by turning the signal Φ3 into an ON state. In this liquid crystal display device, during a period when a given one of the scanning lines GL is selected, the drain driver DRV outputs the a first group of video signals for the first display block BK1, a second group of video signals for the second display group BK2, and a third group of video signals for the third display block BK3 sequentially, in a time-division-multiplexed fashion. This configuration makes it possible to reduce the number of the drain drivers DRV to one third of the number of drain drivers required in a conventional display device.
In the above-explained two liquid crystal display devices, the display area is divided into a plurality of groups, and during one horizontal scanning period in which one of the scanning lines GL, the driver writes video signals into pixels of respective ones of the plural groups sequentially in a time-division-multiplexed fashion. Consequently, it makes possible to drive the drain lines DL larger in number than output terminals of the drain driver DRV.
Specifically, the first conventional display device divides the video signal lines into three groups of a red (R) signal group, a green (G) signal group and a blue (B) signal group, and thereby its drain driver DRV is capable of driving drain lines DL three times as many as the number of its output terminals. The second conventional display device divides the display area DPA into three parts, and thereby its drain driver DRV is capable of driving drain lines DL three times as many as the number of its output terminals.